1. Field of the Invention
The present invention is related to a design of an integrated Dynamic Random Access Memory (DRAM) memory device, especially a design for speeding up the accessing of data in an integrated DRAM memory device.
2. Description of the Related Art
Although the data transfer frequency of DRAM memory devices increases constantly, the access time for data which is randomly accessed remains substantially constant. The decrease of access time of memory cells in a memory device is limited by the physical dimensions and the design and layout of the cell array. Random accessing of data requires selectively changing (activating and deactivating) the wordlines and bitlines frequently which requires a minimum time which can hardly be reduced by shrinking the physical dimensions and/or by changing the memory layout.
The random access speed in memory devices can be increased for example by substantially decreasing the number of cells connected to a single bitline/wordline. However, to keep the overall memory capacity constant, the necessary memory area on chip would substantially increase as the number of bitlines is increased, each being connected with a respective sense amplifier and other support circuit elements. This would be too costly as the overall chip size is substantially increased.
As the random access speed is substantially limited by the bitline and wordline length of a basic memory block, memory arrays with a shrunken bitline length and wordline length are provided when the random access time of the memory block has to be decreased.